Project: Parity Checker Design

Layout-level Design of an 8-bit Parity Checker

Under Prof Anu Gupta | Course Project 2: Analog & Digital VLSI Design | with Hariharan Venkat & Anirudh Subramanian

The project was implemented using the 180 nm node using Microwind and DSCH. We implemented a 16T XOR circuit and used them to implement an 8-bit parity checker circuit. We achieved the following specifications: t_p = 232ps at no load, P = 262μW, A = 2430.4μm².

The project left us with a lot of learning outcomes. The project report can be found here. We plan to reattempt the same problem statement using Cadence and update this page by about April 2023.

First, we started off by deciding the structure of the parity checker in terms of the XOR gate. We noticed that as we increase the number of inputs to each XOR, the number of transistors required shoot up dramatically. Hence, we decided to use 2 input XORs everywhere and arrived at the topology we’ve used.

Then we looked into how we can realize the XOR gate. We looked at the classic NAND implementations, the 12T implementation, a PTL implementation and a wild 3T implementation. After a lot of trial and error, we decided to go with a 16T version, since it was faster, and the voltage levels didn’t get degraded.

We finally drew the layout for the circuit and attempted to simulate it with a load. It was only then that we realized that thanks to a combination of calculation errors and fundamental misconceptions, that our circuit would not operate at the desired frequency of 1 GHz, especially when we include the load.